AT89C51单片机毕业论文

　中英文资料对照外文翻译文献

　英文原文

　Descripti on

　The AT89C51 is a low-power, high-performa nee CMOS 8-bit microcomputer with 4Kbytes of Flash Programmable and Erasable Read Only Memory (PEROM) and 128 bytes RAM. The device is manu factured using Atmel ' s hig h den sity nonv olatile memory tech no logy and is compatible with the industry standard MCS51? instruction

　set and

　pino ut. The chip comb ines a versatile 8-bit CPU with Flash on a mon olithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solutio n to many embedded con trol applicati ons.

　Features:

　? Compatible with MCS -51? Products

　? 4K Bytes of In -System Reprogrammable Flash Memory

　? En dura nee: 1,000 Write/Erase Cycles

　? Fully Static Operatio n: 0 Hz to 24

　MHz

　? Three -Level Program Memory Lock

　128 x 8 -Bit Internal RAM

　? 32 Programmable I/O Lin es

　? Two 16-Bit Timer/Cou nters

　? Six In terrupt Sources

　? Programmable Serial Channel

　? Low Power Idle and Power Down Modes

　The AT89C51provides the following standard features: 4K bytes of Flash, 128 bytes of RAM,32 I/O lines, two 16-bit timer/counters, a five vector two-level in terrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is desig ned with static logic for operati on dow n to zero freque ncy and supports two software selectable power sav ing modes. The Idle Mode stops the CPU while allowing the RAM, timer/coun ters, serial port and in terrupt system to continue fun cti oning.

　The Power Down Modesaves the RAMto nten ts but freezes

　the oscillator disabli ng all other chip fun cti ons un til the next hardware reset.

　Pin Conifigiuratiions

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　Pin Description:

　VCCSupply voltage.

　GNDGrou nd.

　Port 0

　Port 0 is an 8-bit ope n drain bidirecti onal I/O port. As an output port each pin can si nk eight TTL in puts. Whenis are writte n to port 0 pins, the pi ns can be used as high impeda nce in puts.

　Port 0 may also be con figured to be the multiplexed loworder address/data bus duri ng accesses to exter nal program and data memory. In this mode P0 has internal pullups.

　Port 0 also receives the code bytes during Flash programming, and outputs the code bytes duri ng program verificati on. Exter nal pullups are required during program verification.

　Port 1

　Port 1 is an 8-bit bidirecti onal

　I/O port

　with in ter nal

　pullups.

　The Port 1 output buffers can sin k/source four TTL

　in puts.

　Whe n

　1s are written to Port 1 pins they

　are pulled

　high

　by the

　internal

　pullups and can be used as in puts.

　As in puts,

　Port

　1 pins

　that are

　externally being pulled low will source curre nt (IIL) because of the internal pullups.

　Port 1 also receives the low-order address bytes during Flash program ming and verificatio n.

　Port 2

　Port 2 is an 8-bit bidirectional

　I/O port with internal

　pullups.

　The Port 2 output buffers can sin k/source four TTL in puts. Whe n 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as in puts. As in puts,

　Port 2 pins that are

　externally being pulled low will source curre nt (IIL) because of the internal pullups.

　Port 2 emits the high-order address byte

　during fetches from

　external program memoryand during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). I n this applicatio n it uses strong internal pull-ups whe n emitt ing 1s. During accesses to external data memorythat use 8-bit addresses (MOVX@RI), Port 2 emits the contents of the P2 Special Fun cti on Register.

　Port 2 also receives the high-order address bits and some con trol sig nals duri ng Flash program ming and verificatio n.

　Port 3

　Port 3 is an 8-bit bidirectional I/O port with internal

　pullups.

　The Port 3 output buffers can sin k/source four TTL in puts. Whe n

　1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as in puts. As in puts,

　Port 3 pins that are

　externally being pulled low will source current (IIL) because of the pullups.

　Port 3 also serves the functions

　of various special features

　of the AT89C51 as listed below:

　Port

　pin

　alter nate fun cti ons

　P3.0

　rxd (serial in put port)

　P3.1

　txd (serial output port)

　P3.2

　9nt0 (external interruptO)

　P3.3

　9nt1 (external in terruptl)

　P3.4

　t0 (timerO external in put)

　P3.5

　t1 (timerl exter nal in put)

　P3.6

　AWR (external data memory

　write strobe)

　P3.7

　Ard (external data memory read strobe)

　Port 3 also receives some con trol sig nals

　for Flash program ming and verificati on.

　RST

　Reset in put. A high on this pin for two machi ne cycles while

　the oscillator is running resets the device.

　ALE/PROG

　Address Latch En able output pulse for latchi ng the low byte

　of the address during accesses to external memory. This pin is also the program pulse in put (PROG) duri ng Flash program ming.

　In no rmal operati on ALE is emitted at a con sta nt rate of 1/6

　the oscillator freque ncy, and may be used for exter nal tim ing or clock ing purposes. Note, however, that one ALE pulse is skipped duri ng each access to exter nal Data Memory.

　If desired, ALE operati on can be disabled by sett ing bit 0 of

　SFR location 8EH. With the bit set, ALE is active only during a

　MOVXr MOVChstruction. Otherwise, the pin is weakly pulled high.

　Sett ing the ALE-disable bit has no effect if the microc on troller

　is in exter nal executi on mode.

　PSEN

　Program Store En able is the read strobe to exter nal program

　memory.

　Wherthe AT89C51is executing code from external program memory, PSEN is activated twice each machi ne cycle, except that two PSEN activations

　are skipped during each access to external data memory.

　EA/VPP

　External Access En able. EA must be strapped to GND in order

　to en able the device to fetch code from exter nal program memory locatio ns starti ng at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be intern ally latched on reset.

　EA should be strapped to VCC for internal program executions.

　This pin also receives the 12-volt programmi ng en able voltage(VPP) duri ng Flash program ming, for parts that require 12-volt VPP.

　XTAL1

　In put to the inv erti ng oscillator amplifier and in put to the internal clock operati ng circuit.

　XTAL2

　Output from the inverting oscillator amplifier.

　Oscillator Characteristics

　XTAL1 and XTAL2 are the in put and output, respectively, of an inverting amplifier which can be con figured for use as an on-chip oscillator, as shownin Figure 1. Either a quartz crystal or ceramic reson ator may be used. To drive the device from an exter nal clock source, XTAL2 should be left unconn ected while XTAL1 is drive n as show n in Figure 2. There are no requireme nts on the duty cyc